Computer-aided synthesis of a Bidimensional Discrete Cosine Transform chip (Contributo in atti di convegno)

Type

• Contributo in atti di convegno (Classe)
• Prodotto della ricerca (Classe)

Label

• Computer-aided synthesis of a Bidimensional Discrete Cosine Transform chip (Contributo in atti di convegno) (literal)

Anno

• 1989-01-01T00:00:00+01:00 (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#doi

• 10.1109/ISCAS.1989.100331 (literal)

Alternative label

• V. Rampa, G. De Micheli (1989)
  Computer-aided synthesis of a Bidimensional Discrete Cosine Transform chip
  in IEEE International Symposium on Circuits and Systems 1989 (ISCAS'89), Portland (USA), 8-11 May
  (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori

• V. Rampa, G. De Micheli (literal)

Pagina inizio

• 220 (literal)

Pagina fine

• 225 (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#altreInformazioni

• IDS Number: BR31U (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#url

• http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=100331 (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#titoloVolume

• Proceedings of the IEEE International Symposium on Circuits and Systems 1989 (ISCAS'89) (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#volumeInCollana

• 1 (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#pagineTotali

• 6 (literal)

Note

• IEEE Xplore digital library (literal)
• ISI Web of Science (WOS) (literal)
• Google Scholar (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni

• CSTS-CNR, c/o Politecnico di Milano, Milano; CSL, Stanford University, Stanford (literal)

Titolo

• Computer-aided synthesis of a Bidimensional Discrete Cosine Transform chip (literal)

Abstract

• The design of an integrated circuit implementing a bidimensional discrete cosine transform (BDCT) is presented. Such a circuit can be used to remove redundancy of video information in low-rate transmission channels and to perform video compression for image storage. The chip architecture is motivated by the fact that the BDCT equations can be solved row-by-row and column-by-column by a simpler monodimensional DCT (MDCT). Therefore, the chip structure is partitioned into three stages: the first and the last one implement MDCTs, while the second stage is a shared memory array. The DCT design was achieved by means of the OLYMPUS synthesis system, an experimental suite of synthesis tools. A parameterized behavioral description of the monodimensional DCT operator was specified in a high-level description language, HardwareC, in terms of concurrent processes communicating through a shared medium. The circuit layer was synthesized automatically from this description. (literal)

Editore

• IEEE - Institute of Electrical and Electronics Engineers (Editore)

Prodotto di

• Reti wireless integrate per accesso ad alta velocita' (ICT.P07.005.001) (Modulo)
• Istituto di elettronica e di ingegneria dell'informazione e delle telecomunicazioni (IEIIT) (Istituto)

Autore CNR

• VITTORIO RAMPA (Unità di personale interno)

Incoming links:

Prodotto

• Istituto di elettronica e di ingegneria dell'informazione e delle telecomunicazioni (IEIIT) (Istituto)
• Reti wireless integrate per accesso ad alta velocita' (ICT.P07.005.001) (Modulo)

Autore CNR di

• VITTORIO RAMPA (Unità di personale interno)

Editore di

• IEEE - Institute of Electrical and Electronics Engineers (Editore)