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Low Complexity Multiuser Detectors for TD-SCDMA Systems: Design and Implementation (Contributo in atti di convegno)

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Low Complexity Multiuser Detectors for TD-SCDMA Systems: Design and Implementation (Contributo in atti di convegno) (literal)

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A. Bifano, V. Rampa (2004)
Low Complexity Multiuser Detectors for TD-SCDMA Systems: Design and Implementation
in 12th International Conference on Software, Telecommunications & Computer Networks, (SoftCOM 2004), Dubrovnik and Split, Croatia and Venice, Italy, 10-13/10/2004
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http://www.fesb.hr/SoftCOM/2004/ Nel 2004 gli atti della conferenza erano disponibili solo in formato cartaceo. (literal)

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SoftCOM 2004, Proceedings of the 12th International Conference on Software, Telecommunications & Computer Networks (literal)

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In TD-SCDMA systems, multiuser detection (MUD) algorithms are adopted at the base station to reduce multiple access (MAI) and inter-symbol interference (ISI). MMSE MUD algorithms solve a linear problem where the system matrix has a block Toeplitz shape. While exact inversion techniques impose an intolerable computational load, reduced complexity algorithms may be efficiently employed. In this paper we will introduce a novel detector scheme that uses the block Bareiss algorithm and compare it in terms of complexity, performance figures and HW feasibility issues with respect to well know algorithms found in literature. Finally, the most effective algorithm will be implemented using standard VHDL (VHSIC Hardware Description Language) techniques and a FPGA (Field Programmable Gate Array) device will be presented. (literal)

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Dipartimento di Elettronica e Informazione, Politecnico di Milano; Istituto di Elettronica e di Ingegneria dell'Informazione e delle Telecomunicazioni, CNR (literal)

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Low Complexity Multiuser Detectors for TD-SCDMA Systems: Design and Implementation (literal)

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Abstract

In TD-SCDMA systems, multiuser detection (MUD) algorithms are adopted at the base station to reduce multiple access (MAI) and inter-symbol interference (ISI). MMSE MUD algorithms solve a linear problem where the system matrix has a block Toeplitz shape. While exact inversion techniques impose an intolerable computational load, reduced complexity algorithms may be efficiently employed. In this paper we will introduce a novel detector scheme that uses the block Bareiss algorithm and compare it in terms of complexity, performance figures and HW feasibility issues with respect to well know algorithms found in literature. Finally, the most effective algorithm will be implemented using standard VHDL (VHSIC Hardware Description Language) techniques and a FPGA (Field Programmable Gate Array) device will be presented. (literal)

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